Integrated circuit devices typically have a number of input/output pins to generate output signals. Output signals of an integrated circuit are typically switched simultaneously in response to a clock signal. Such simultaneously switching of outputs results in large transient currents which are often difficult to control. In particular, power and ground noise, which comprises undesirable signals on a line, is generated in on-chip power and ground buses when the signals at the outputs switch logic states simultaneously. When a significant number of drivers switch at the same time, an increased current draw on the power supply may cause a droop or negative spike in the voltage supply to the chip. This dip in power supply voltage may propagate as noise through both active and quiet drivers, and may cause false switching in the system. With system speeds increasing and the demands to transmit more data, destructive switching noise has become a significant concern.
Jitter in a clock signal, caused by thermal noise or external interference through the power or ground lines may also have a significant impact on the operation of a circuit. For example, period jitter, also known as “edge-to-edge” jitter, is the deviation in time of any clock period from the ideal clock period. Period jitter results in phase variations with respect to a perfect reference clock or data signal as a result of noise. The period jitter is usually measured as the difference between the longest period and the shortest period. Accommodating for period jitter is necessary to ensure that there is adequate setup time for all of the signals. Jitter may also arise from simultaneous switching of internal logic that are not part of the input/output (I/O) elements, such as configurable logic blocks (CLBs) or blocks of Random Access Memory (BRAMs) of a programmable logic device (PLD), which will be described in more detail below. Accordingly, it is necessary to overcome large transients resulting from simultaneous switching noise or thermal noise resulting in clock jitter, and provide noiseless power and ground connections.
Supply noise suppression has been done in conventional circuits with passive components, such as capacitors connected across the power supply rail and ground. The capacitor provides a shunt path for transient noise on the supply rail to ground to minimize transient voltage amplitude, while storing and providing a local charge to minimize voltage droop. However, the performance of passive devices is limited by their parasitic inductance, series resistance, and capacitance which are functions of the type of material used, packaging, temperature, DC bias, and operating frequency. Further, because a capacitor becomes inductive past its resonant frequency, a given capacitor value is typically optimal for one resonant frequency, but not over a wide range of frequencies. In addition, due to parasitic resistance and inductance, the performance of passive devices tends to degrade rapidly at frequencies above 100 Mhz.
Accordingly, there is a need for an improved method of and circuit for suppressing noise in a circuit.